FM demodulator using multiplier to which delayed and undelayed input signals are applied

ABSTRACT

An FM signal demodulator including a multiplier having a pair of input terminals and an output terminal. A signal coupling circuit is connected between a circuit input terminal and one of the input terminals of the multiplier to couple an FM signal to the multiplier, and a delay line and a phase shifter are connected in cascade between the signal input terminal and the other input terminal of the multiplier. A low pass filter is connected to the output terminal of the multiplier to allow the demodulated signal to reach the circuit output terminal.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to an FM demodulator and moreparticularly to an FM demodulator using a multiplier.

2. Description of the Prior Art

In the past, ratio detectors have been generally used as FMdemodulators. Recently, so-called quadrature FM detectors, which employa multiplier, have come to be used as FM detectors because thequadrature FM detector has a wide linear operation range and is easilyproduced as an integrated circuit. In quadrature FM detectors, one ofthe FM signals is applied directly to the multiplier and the other FMsignal is applied to the multiplier through a delay circuit. The amountof phase-shift produced by the delay circuit is changed in response tothe frequency of the signal applied thereto. The multiplier outputsignal, which is the product of both of the signals, is then passedthrough a low pass filter and emerges as the demodulated signal.

With this kind of FM demodulator, however, it is well known that itsdetected output signal amplitude is proportional to the amount of delayproduced by its delay circuit, and the center frequency of thedemodulator is also a function of the amount of delay of the delaycircuit.

Accordingly, the amount of delay in a prior art quadrature FM detectoris set so as to make the detected output level optimum, and if thecenter frequency is then adjusted so as to make the distortion ratio ofthe demodulator minimum, the detected output level will have deviatedfrom the otpimum value. Thus, the output level of the demodulated signaland the center frequency of a prior art FM demodulator using amultiplier cannot be adjusted independently.

OBJECTS AND SUMMARY OF THE INVENTION

It is an object of the present invention to provide an improved FMdemodulator free from the above-described defect of the prior art.

It is another object of the invention to provide an FM demodulator whichincludes only the addition of a phase shifter to permit its detectedoutput level and center frequency to be adjusted independently.

In accordance with the present invention, an FM demodulator circuit thatincludes a multiplier has a circuit input terminal to which a frequencymodulated signal is supplied. The circuit input terminal is connected to(or comprises) one of the input terminals of the multiplier. A low passfilter is connected to the output terminal of the mulitplier to filterout undesired high frequency RF or IF components so as to leave only thedemodulated signal. A circuit that includes a series connection of adelay line and a phase shifter connects the signal input terminal of thecircuit to the other input terminal of the multiplier.

Further objects, features, and advantages of the present invention willbe apparent from the following description taken in conjunction with thedrawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing an embodiment of an FM demodulatoraccording to the present invention.

FIGS. 2A and 2B are graphs used for explaining the embodiment of theinvention shown in FIG. 1.

FIG. 3 is a circuit diagram showing another embodiment of the invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

An example of the FM demodulator according to the present invention willbe now described with reference to FIGS. 1, 2A, and 2B.

The circuit in FIG. 1 includes a circuit input terminal IN to which anFM signal is applied. This FM signal is applied to a delay line 4, theamount of delay of which is varied in response to the frequency of theFM signal. In the example of FIG. 1, a phase shifter 8 is connected tothe output side of the delay line 4. The phase shifter 8 will bedescribed later, and only the effect of the delay line 4 will beconsidered at this point. A multiplier 9 receives the FM signal directlyfrom the input terminal IN and also receives the output signal of thedelay line 4. The output signal of the multiplier 9 is taken from itsoutput terminal 10 and fed through a low pass filter 12 to an outputterminal OUT at which the demodulated output siganl of the FM signal isobtained.

The FM signal e₁ (t) applied to the input terminal IN can be expressedby the following equation (1)

    e.sub.1 (t) = sin(2πft )                                (1)

where f is the instantaneous frequency and t is the time. The outputsignal e₂ (t) from the delay line 4 is expressed as follows:

    e.sub.2 (t) = sin [2πft+φ(2 πf)]                 (2)

Thus, if the phase shifter 8 is omitted the multiplied output signal e₃(2πf), after carrier frequency components have been filtered out, can beobtained at the output terminal OUT and expressed as follows:

    e.sub.3 (2πf) = G · e.sub.1 (t) · e.sub.2 (t) =G/2 cos [φ(2πf)]                                           (3)

where G is the detection gain.

If the phase shifting amount φ(2πf) is expressed as follows:

    φ(2πf) = 2πAf                                    (4)

where A is a proportional constant delaying amount, the signal e₃ (2πf)is expressed as follows:

    e.sub.3 (2πf) = G/2 cos (2πAf)                       (5)

This signal e₃ (2πf) is shown in FIG. 2A by a cosine curve S₁.

Further, the differentiated gain of the signal e₃ (2πf) is expressed asfollows: ##EQU1##

This differentiated gain is shown in FIG. 2B by a curve S₂.

If the carrier frequency f₀ is selected to be on the most nearly linearportion of the differentiated gain characteristic curve, which is withina few degrees of those points at which the cosine curve S₁ crosses thezero axis, the carrier frequency must be selected to make the factor sin(2πAf₀) a maximum or minimum at such points, which are identified aspoints a, b, etc. The factor sin(2πAf) is a maximum when sin(2πAf) = sinπ/2. If that is to be true, 2πAf must be equal to π/2, which requiresthat f = 1/4A. Thus, if the carrier frequency f₀ is expressed as ageneral formula, the following equation (7) is obtained:

    f.sub.0 = 1/A · (2n - 1)/4                        (7)

where n is 1, 2, 3, etc., corresponding to any of the points at whichthe cosine curve S₁ crosses the zero axis.

As may be apparent from equation (5) above, the level of the outputsignal is in proportion to the proportional constant delaying amount A.Thus, if it is desired that the carrier frequency f₀ be selected to havean optimum value as described above, and the level of the demodulatedoutput signal is also selected at a desired value, the values f₀ and Acan not be selected independently of each other which is inconventient.

In order to overcome the above problem, the phase shifter 8 is providedin the example of the present invention shown in FIG. 1 and is shown tobe connected to the output side of the delay line 4 and in seriestherewith. Alternatively, the phase shifter 8 could be connected at theinput side of the delay line 4.

If the FM modulated signal e₁ (t) is as expressed by the equation (1),the output signal e₂ (t) of the phase shifter 8 can be expressed by thefollowing equation (8):

    e.sub.2 (t) = sin[2πft + φ.sub.1 (2πf) + φ.sub.2 ](8)

in which the term φ₁ (2πf) represents the phase of a function of theinstantaneous frequency f of the FM medulated signal based upon theoperation of the delay line 4 and φ₂ is a constant phase independent ofthe frequency f and based upon the effect produced by the phase shifter8. Thus, the multiplied output signal e₃ (2πf) obtained at the outputterminal OUT becomes as follows:

    e.sub.3 (2πf) = G · e.sub.1 (t) · e.sub.2 (t) = G/2 cos[φ.sub.1 (2πf) + φ.sub.2 ]                  (9)

If the term φ₁ (2πf) is expressed as

φ₁ (2πf) = 2πAf

the signal e₃ (2πf) becomes as follows:

    e.sub.3 (2πf) = G/2 cos (2πAf = φ.sub.2)

Thus, its differentiated gain [de₃ (2πf)]/d(2πf)] is expressed asfollows: ##EQU2##

In order to select the carrier frequency f₀ on the most linear portionsof the differentiated gain characteristic curve, the carrier frequencyf₀ must be selected to make the value of sin(2πAf + φ₂) maximum orminimum. Thus, in a manner corresponding to the previous analysis, thecarrier frequency f₀ can be expressed as follows: ##EQU3## where n = 1,2, 3, . . . .

Since the level of the demodulated output signal is in proportion to theproportional constant delay A, even if the constant A is selected tomake the demodulated output level optimum, the carrier frequency f₀ canstill be selected to have an optimum value independently of thedemodulated output level as may be apparent by varying φ₂ in the lastequation.

For example, if the intermediate frequency of an FM radio receiver is10.7 MHz, if the delay line 4 is selected to produce a delay of 140 nsec, the shifting amount φ₂ of the phase shifter 8 is selected to be90°.

Another embodiment of the present invention will be hereinbelowdescribed with reference to FIG. 3. In FIG. 3, an input terminal 1 issupplied with an FM signal. This input terminal 1 is connected to theinput side of an amplifier circuit 2, which is a differential amplifiercircuit having transistors Q₁ and Q₂ as amplifying elements. A thirdtransistor Q₃ serves as a constant current source. The input terminal 1is connected to the base electrode of the transistor Q₁. The next stageof the amplifier circuit 2 is a buffer amplifier circuit 3, whichconsists of transistors Q₄ and Q₅ connected as emitter followers. Thebase electrodes of the latter transistors are connected to the collectorelectrodes of the transistors Q₁ and Q₂, respectively. A delay circuit,or line, 4 is connected to the emitter of the transistor Q₅ at theoutput side of the buffer amplifier circuit 3. The amount of delay is afunction of the frequency change of the FM signal. This delay line couldbe, for example, an L-C type low pass filter, as shown. The capacitiesand inductances of respective capacitors and coils in the delay line 4are selected as C/2, C, . . . C, C/2 and L, L, . . . L, L, respectively.

The output of the delay line 4 is connected to a phase shifter 8 whichshifts the phase of the applied signal by a substantially constantamount for the frequency variation of the FM signal. The phase shifter 8is an all pass filter in this example and includes a transistor Q₆,having its base electrode connected to the output side of the delay line4 to receive the delayed signal therefrom. A resistor 6 and a capacitor7 are connected in series between the collector and emitter electrodesof the transistor Q₆, and the connection point between the resistor 6and capacitor 7 is the output terminal of the phase shifter 8. Theamount of phase shift can be varied by changing, for example, theresistance of the resistor 6. In the example shown in FIG. 3, the phaseshifter 8 is connected to the output side of the delay line 4, but it ispossible for the delay 4 to be connected, instead, to the output side ofthe phase shifter 8 with the same effect.

Following the phase shifter 8 is a buffer amplifier circuit 5. Thiscircuit includes an input stage that operates as an impedance convertingcircuit and is formed of a transistor Q₇ connected as an emitterfollower. The amplifier 5 also includes a differential amplifier circuitconsisting of amplifying transistors Q₈ and Q₉ and a constant currenttransistor Q₁₀. In this case, the base electrode of the transistor Q₇ isconnected to the connection point between the resistor 6 and thecapacitor 7 and its emitter is connected to the base of the transistorQ₈. The collector electrodes of the transistors Q₈ and Q₉ are connectedto input terminals t₁ and t₂ of a multiplier 9.

The FM signal from the buffer amplifier 3 as well as the delayed FMsignal from the buffer amplifier circuit 5 are applied to the multiplier9 which multiplies one of these signals by the other to produce ademodulated signal.

The multiplier 9 is shown to include transistors Q₁₁ to Q₁₇. Thetransistors Q₁₁ to Q₁₃ and Q₁₇ form a differential amplifier circuit atthe input side, and the transistors Q₁₄ to Q₁₇ form a differentialamplifier at the output side, respectively. The transistors Q₁₁ and Q₁₂,and the transistors Q₁₄ in this embodiment serve as amplifyingtransistors, the transistors Q₁₃ and Q₁₆ serve as variable currenttransistors, and the transistor Q₁₇ serves as a constant currenttransistor, respectively.

The FM signals of opposite polarity are differentially fed from theamplifier 2 through the buffer amplifier circuit 3 to the baseelectrodes of the transistors Q₁₃ and Q₁₆ of the multiplier 9,respectively, and the delayed FM signals of opposite polarity arerespectively fed from the buffer amplifier 5 to the base electrodes ofthe transistors Q₁₁ and Q₁₅ through the input terminal t₁, and to thebase electrodes of transistors Q₁₂ and Q₁₄ through the input terminalt₂. An output terminal 10 is connected to the collector electodes of thetransistors Q₁₂ and Q₁₅, and the demodulated signal is obtainedtherefrom. This demodulated signal may then be passed through asmoothing filter like the filter 12 in FIG. 1.

In FIG. 3, the power supply has a positive terminal +B and a negativeterminal -B.

The theory of operation of the circuit shown in FIG. 3 is substantiallythe same as that of the circuit shown in FIG. 1, so that its descriptionwill be omitted.

It will be apparent from the foregoing, that the FM demodulator of thepresent invention includes a delay device or line that delays the signalapplied to it by an amount that varies in response to the frequencyvariation of the FM signal. The demodulator also includes a phaseshifter whose phase-shifting amount is substantially constant for thefrequency variation of the FM signal. It further includes a multiplierin which the FM signals and the delayed FM signals obtained by supplyingthe FM signals to the series circuit of the delay device and the phaseshifter are multiplied together to produce the demodulated signal. As aresult, the optimum angular frequency at which the differentiating gainis substantially flat and the demodulated output level can be selectedfreely and independently of each other.

Further, with the FM demodulator of the invention the scattering of thetotal phase-shifting amount or delaying amount of the series circuit ofthe delay device and the phase shifter can be corrected, and the delaycharacteristics can be improved.

It is not necessary that the delay device 4, phase shifter 8 andmultiplier 9 be limited to the embodiments described above and shown inthe drawings; other suitable embodiments could be used, instead.

It will be apparent that modifications and variations could be effectedby one skilled in the art without departing from the spirit or scope ofthe novel concepts of the present invention, so that the true scope ofthe invention should be determined only by the following claims.

What is claimed is:
 1. An FM demodulator comprising:a. a signal inputterminal supplied with a frequency modulated signal; b. a multiplierhaving a pair of input terminals and an output terminal; c. a low passfilter connected to the output terminal of said multiplier to filter theoutput signal of the multiplier; d. coupling means for coupling saidsignal input terminal to one of said input terminals of said multiplier;and e. a series circuit comprising a delay line and a phase shifterconnected between said signal input terminal and the other of the inputterminals of said multiplier.
 2. An FM demodulator according to claim 1,in which said delay line comprises an L-C type low pass filter.
 3. An FMdemodulator according to claim 1, in which said phase shifter comprisesan all pass filter circuit.
 4. An FM demodulator according to claim 3,in which said all pass filter comprises:a. a transistor having base,emitter and collector electrodes, the base being connected to the outputof said delay line; b. a collector load resistor and an emitter loadresistor connected to the collecter and emitter, respectively; and c. asecond series circuit comprising a variable resistor and a capacitorconnected between the collector and emitter electrodes of saidtransistor, the connection point between the variable resistor andcapacitor comprising an output terminal of said all pass filter.
 5. AnFM demodulator according to claim 1, in which said multiplier comprisesat least three cascade-connected differential amplifiers.
 6. An FMdemodulator according to claim 1, further including a buffer amplifierconnected between said signal input terminal and the input side of saidfirst-named series circuit comprising the delay line and the phaseshifter.
 7. An FM demodulator according to claim 6, further including afurther buffer amplifier connected between the output side of saidfirst-named series circuit and the other of said input terminals of saidmultiplier.